Electronics devices and capabilities have grown common in daily life. Along with personal computers in the home, many individuals carry more than one productivity tool for various and sundry purposes. Most personal productivity electronic devices include some form of non-volatile memory. Cell phones utilize non-volatile memory in order to store and retain user programmed phone numbers and configurations when the power is turned off. PCMCIA cards utilize non-volatile memory to store and retain information even when the card is removed from its slot in the computer. Many other common electronic devices also benefit from the long-term storage capability of non-volatile memory in un-powered assemblies.
Non-volatile memory manufacturers that sell to the electronic equipment manufacturers require testers to exercise and verify the proper operation of the memories that they produce. Due to the volume of non-volatile memories that are manufactured and sold at consistently low prices, it is very important to minimize the time it takes to test a single part. Purchasers of non-volatile memories require memory manufacturers to provide high shipment yields because of the cost savings associated with the practice of incorporating the memory devices into more expensive assemblies with minimal or no testing. Accordingly, the memory testing process must be sufficiently efficient to identify a large percentage of non-conforming parts and preferably all non-conforming parts in a single test process.
As non-volatile memories become larger, denser and more complex, the testers must be able to handle the increased size and complexity without significantly increasing the time it takes to test them. As memories evolve and improve, the tester must be able to easily accommodate the changes made to the device. Another issue specific to testing non-volatile memories is that repeated writes to cells of the memories can degrade the overall lifetime performance of the part. Non-volatile memory manufacturers have responded to many of the testing issues by building special test modes into the memory devices. These test modes are not used at all by the purchaser of the memory, but may be accessed by the manufacturer to test all or significant portions of the memories in as little time as possible and as efficiently as possible. Some non-volatile memories are also capable of being repaired during the test process. The tester, therefore, should be able to identify; a need for repair, a location of the repair, the type of repair needed, and then must be able to perform the appropriate repair. Such a repair process requires a tester that is able to detect and isolate a specific nonconforming portion of the memory. In order to take full advantage of the special test modes as well as the repair functions, it is beneficial for a tester to be able to execute a test program that supports conditional branching based upon an expected response from the device.
From a conceptual perspective, the process of testing memories is an algorithmic process. As an example, typical tests include sequentially incrementing or decrementing memory addresses while writing xe2x80x9c0xe2x80x9d""s and xe2x80x9c1xe2x80x9d""s into the memory cells. It is conventional for tests to include writing patterns into the memory space such as checkerboards, walking xe2x80x9c1xe2x80x9d""s and butterfly patterns. A test developer can more easily and efficiently generate a program to create these patterns with the aid of algorithmic constructs. A test pattern that is algorithmically coherent is also easier to debug and use logical methods to isolate portions of the pattern that do not perform as expected. A test pattern that is generated algorithmically using instructions and commands that are repeated in programming loops consume less space in tester memory. Accordingly, it is desirable to have algorithmic test pattern generation capability in a memory tester.
Precise signal edge placement and detection is also a consideration in the effectiveness of a non-volatile tester. In order to capture parts that are generally conforming at a median while not conforming within the specified margins, a non-volatile memory tester must be able to precisely place each signal edge relative in time to another signal edge. It is also important to be able to precisely measure at which point in time a signal edge is received. Accordingly, a non-volatile memory tester should have sufficient flexibility and control of the timing and placement of stimuli and responses from the memory device under test.
In order to properly test larger memories the tester must be equipped with a significant amount of memory to properly store all of the test vectors that comprise a single test program. The tester must also be faster than the memory it is testing in order to properly characterize and test the timing characteristics of the IC. Historically, memory testers use SRAM for program storage. The SRAM is embedded into the tester ASIC to achieve the greatest tester efficiency. SRAM is useful because it exhibits a minimum latency permitting accurate reproduction of timing conditions for testing purposes. SRAM, however, is costly. As test programs increase in size, a natural solution is to merely increase the amount of embedded SRAM in order to accommodate the entire test program. SRAM, however, is expensive. It is difficult to cost-effectively embed a sufficient amount of SRAM into the tester ASIC to store the entire test program. An alternative to the SRAM is DRAM. Disadvantageously, there is a significant read latency associated with DRAM. This read latency does not permit execution of program instructions directly if it is desired to maintain precise timing. The DRAM is, however, advantageously used for storage of program instructions for use at a later time. There is a need, therefore, for a method and apparatus of using the cost effective DRAM for storage of executable software while optimizing tester performance through appropriate management of the SRAM and DRAM memories.
A method for managing execution of a program downloads a file containing a called pattern and at least one dependency of the called pattern. The method then stores contents of the file in a secondary memory and initiates execution of the called pattern. Test dependencies of the called pattern are identified after which the process selectively copies the called pattern and the identified test dependencies into a primary memory. Finally, the pattern is executed.
A method for managing execution of a program, wherein the program initiates execution of one or more patterns and one or more of the patterns depend upon one or more software units, downloads a test file into a secondary memory. The test file contains the patterns and the software units that are downloaded into the secondary memory. The process then initiates execution of a called pattern from the available patterns and determines dependencies of the called pattern. The process allocates space in a primary memory for the called pattern and the dependencies. The called pattern and the dependencies are then selectively copied from the secondary memory to the primary memory prior to executing the called pattern.
An apparatus for calculating a new address location comprises a comparator accepting an old address and a threshold address and an output value indicating whether the old address is greater than the threshold address. An arithmetic operator accepts the old address and an address offset value and generates a sum of the old address and the address offset value. A selector accepts the old address and the sum and selects an output of the selector based upon the comparator output value. The output of the selector is the new address location.
A method for managing development of a program in a tester stores one or more test patterns in a memory, the one or more test patterns including a first section and a remaining section. The method then moves the first section to a different location in the memory and offsets calls in the first section to branching destinations in said first section. The process then inserts one or more instructions in a position adjacent to the different location in the memory, and offsets calls in the remaining section to branching destinations in the remaining section.
A method for managing development of a program in a tester stores at least two patterns in a memory, the patterns populating the memory in a first section, a second section, and a remaining section. The process then deletes the second section and moves the remaining section to be contiguous with the first section. Calls in the first section to branching destinations in said remaining section are offset and then calls in the remaining section to branching destinations in said first section are offset.
Advantageously, a method and apparatus used in a memory tester according to the teachings of the present invention permits efficient and cost effective use of DRAM in conjunction with SRAM to achieve optimal program storage and performance.